MPC8360EVVAJDGA(NXP USA Inc.) Description
Additional information about the MPC8360EVVAJDGA: This section describes a high-level overview including features and
general operation of the MPC8360E/58E PowerQUICC II Pro processor.
A major component of this device is the e300 core, which includes
32 Kbytes of instruction and data cache and is fully compatible with the
Power Architecture 603e instruction set. The new QUICC Engine
module provides termination, interworking, and switching between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine module’s enhanced interworking eases
the transition and reduces investment costs from ATM to IP based systems. The other major features include a dual DDR
SDRAM memory controller for the MPC8360E, which allows equipment providers to partition system parameters and data in
an extremely efficient way, such as using one 32-bit DDR memory controller for control plane processing and the other for data
plane processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also offers a 32-bit PCI
controller, a flexible local bus, and a dedicated security engine.